The AI Infrastructure Bottleneck as a Semiconductor Constraint Rotation

The AI infrastructure bottleneck has done what it always does. It has moved.

On March 27, 2026, Nvidia (NVDA) committed roughly $2 billion of equity into Coherent (COHR) and another $2 billion into Lumentum (LITE), then layered multibillion-dollar EML laser purchase agreements on top. The Futurum Group writeup of those deals noted that non-Nvidia transceiver buyers were quoted lead times past 2027 within weeks. That is the same fingerprint memory showed eighteen months earlier and CoWoS advanced packaging showed before that. Optical interconnect is now contractually allocated.

The episode that prompted this piece, The Real Eisman Playbook episode 63 with Bernstein analyst Stacy Rasgon, frames AI’s pull on semiconductors as a rolling sequence: accelerators, then memory, then optical, then power semiconductors, then CPUs.

“AI has gotten so big, it is now dragging everything along with it,” Rasgon told Steve Eisman on the show. “One at a time all of these different parts of the industry have sort of become the constraint.”

The rotation is real. The interesting question is whether a public-equity investor can still front-run it inside the chip sector at all.

The bull case

The sequence is empirically there. Memory was a sideshow seven months ago and is now the loudest name on the tape. According to VanEck, the SMH semiconductor ETF returned about 66% year to date through early June 2026, with MU and HBM-exposed names doing most of the lifting. The iShares SOXX quote shows the broader basket closer to 79% over the same window.

Inside that move, Micron (MU) has roughly doubled. The Q1 FY2026 Micron earnings release guided gross margin into the high-60s, a level the company has never sustained as a pure DRAM/NAND vendor. Bernstein, which is Rasgon’s own desk, called it the largest pricing upcycle in the memory sector and lifted the price target to $330.

UBS went further: from $535 to $1,625, the new Street high, arguing consensus is still modeling memory on legacy cyclical multiples while HBM4 is already booked for 2027.

The mechanism is mundane and that is what makes it durable. A bit of HBM consumes roughly three times the wafer area of a bit of DDR5, and all three DRAM houses have pre-sold their 2026 capacity. The bull writeup at Seeking Alpha argued the cycle has stopped being cyclical because the unit economics broke. New fab capacity takes three to four years to come online. The demand is contracted today.

The bear case

There are two versions of the bear case and they do not say the same thing.

The narrow bear is about price. Seeking Alpha‘s Julian Lin pointed out that MU‘s RSI recently printed 90, the most overbought reading since September 1995, which sat directly atop the last memory-cycle top. Roughly three-quarters of Micron’s revenue is still commodity DRAM and NAND.

The Motley Fool added the historical pattern: tight supply, double-ordering for allocation, $20-25 billion of capex committed on three-year demand forecasts, new fabs delivered into a softening market, margin implosion.

The wider bear is more uncomfortable for the front-run-the-next-link thesis. Rasgon himself, in the 24/7 Wall St. writeup of his Bernstein note, argued the constraints are not serial. TSMC foundry capacity, CoWoS packaging, HBM, and optics are all running at max at the same time. There is no tidy queue.

And the binding constraint, per Omdia via Manufacturing Dive, has already jumped past silicon. The gating link in 2026 is the grid. Transformer and switchgear lead times stretch four to seven years in Northern Virginia, Phoenix, and Dallas, and roughly 11 GW of announced 2026 capacity is stuck waiting for an interconnect, not a chip.

What the data shows

The constraint-rotation picture, drawn from the public numbers we can verify:

Link in the chain	Ticker	What changed in 2025-26	Where the rent goes
Accelerators	NVDA	Solved, now allocator of downstream supply	Already priced
Memory / HBM	MU	Margins to ~68%, capacity sold through 2026	Repricing in progress
Optical interconnect	COHR, LITE	Locked to Nvidia by equity plus offtake	Largely captured
Custom AI silicon	AVGO	Record AI quarter	Already in the multiple
Power equipment	GEV, ETN, VRT	4-7 year interconnect queues	Open

The Deloitte 2026 semiconductor outlook reads the same way. Every node of the chip stack is binding at once, and the marginal new dollar of AI capex is increasingly chasing power, cooling, and land.

The fresh angle

The bottleneck sequence is real. Public-equity participation in it inside semiconductors is mostly over.

NVDA was repriced before most retail investors heard the word “accelerator.” MU is the last link where the cheap money was still on the table six months ago, and it has run. COHR and LITE are now contractually allocated, which means the supply rent accrues to Nvidia’s customers, not to the optical names’ public float.

The link that still has a queue, a capex cycle that has not been compressed by the AI demand pull yet, and listed equity with discount embedded is the non-semiconductor stack: GE Vernova (GEV), Eaton (ETN), Vertiv (VRT), and adjacent grid and IPP names. That is where the rotation actually points next. Calling 2026’s AI infrastructure bottleneck a semiconductor constraint rotation is accurate as history and misleading as a trade idea.

What would change our mind

• A clear DeepSeek-style efficiency break that cuts HBM-per-token demand by half before HBM4 ships. That collapses the memory thesis and validates the cyclical-top bears.
• Grid interconnect queues clearing materially faster than the 4-7 year quote, which would re-anchor the binding constraint back into chips and re-rate COHR, LITE, and CoWoS-adjacent names.
• Hyperscaler capex guides cut by 20% or more in any single quarter, which would unwind the contracted-not-paid concern across MU and the optical pair simultaneously.

What this does not tell you

The piece does not tell you which point in the cycle Micron’s RSI 90 actually marks. It correlated with a top in 1995. It does not have to in 2026. The mechanism is different now. In 1995, end customers were hoarding inventory. Today, the contracts are signed, but the contracts can still be renegotiated if cloud capex resets.

It also does not tell you the exact magnitude of the optical lock-up. The Coherent and Lumentum deals are public; the carve-outs for non-Nvidia customers are not.

And it does not tell you which power and grid names are already priced for the rotation. GEV is up materially in 2026 too. The fresh-angle observation is the direction of the rotation, not a clean entry point.

FAQ

Is the bottleneck sequence (accelerators, memory, optical, power, CPUs) a real pattern or hindsight?

Both. It is a real description of which link has been the constraint at each point in the last three years. It is not a clean forecast. Rasgon himself argues the constraints now bind simultaneously, which limits the sequence’s predictive value going forward.

Is Micron still attractive after doubling?

We do not give buy and sell calls. The bull case (UBS’s $1,625 target, sold-out HBM through 2026, Bernstein at $330) and the bear case (RSI 90, commodity DRAM still about 75% of revenue, the 1995 analogue) are both legitimate and need to be sized against each other.

What is the single highest-conviction observation here?

The binding constraint has moved off silicon and onto the grid. That is Omdia’s read, and it is consistent with the lead times being quoted on transformers and switchgear in U.S. data center markets right now.