EUV Lithography Bottleneck Impact: The AI Constraint Is Real, But It Is Moving

ASML (ASML) is the cleanest bottleneck story in AI hardware. One company makes the EUV lithography tools needed for the most advanced logic chips, and those tools cannot be stamped out like servers. In 2025, ASML reported €32.7 billion ($35.6 billion) of total net sales, €9.6 billion ($10.5 billion) of net income, and €38.8 billion ($42.3 billion) of backlog, ASML’s Q4 2025 results show.

That is why Dylan Patel’s EUV thesis gets attention. His claim is not that AI demand is strong. Everyone can see that. His sharper claim is that AI compute eventually runs into a machine-count problem: not enough EUV tools, not enough leading-edge wafers, not enough frontier chips.

I think the supply constraint is real. I also think the simple version is too neat. The semiconductor industry rarely accepts a single bottleneck as final. It moves the problem. First to multi-patterning. Then to chiplets. Now to advanced packaging, power delivery, memory bandwidth, and software efficiency.

Key facts at a glance

• ASML reported 2025 total net sales of €32.7 billion ($35.6 billion), up from €28.3 billion ($30.8 billion) in 2024, according to ASML’s Q4 2025 release and ASML’s Q4 2024 release.
• ASML’s backlog was €38.8 billion ($42.3 billion) at the end of 2025, and Q4 2025 net bookings were €13.2 billion ($14.4 billion), including €7.4 billion ($8.1 billion) of EUV bookings, the same ASML release said.
• ASML guided 2026 sales to €34 billion ($37.1 billion) to €39 billion ($42.5 billion), with a 51% to 53% gross margin, ASML’s Q4 2025 release said.
• Patel’s model frames EUV as a later-decade AI compute ceiling, with roughly 3.5 EUV tools needed per gigawatt of AI compute and a possible 200 gigawatt cap by 2030, according to the Dwarkesh interview transcript and SemiAnalysis-linked summary.
• Listed options data checked on 2026-06-18 showed ASML IV rank at 74.8 and IV percentile at 88.4, with an 11.3392% earnings implied move for the 2026-07-17 expiry. That is positioning context, not proof of the thesis.
• Public market prices checked on 2026-06-23 showed ASML at $1,778.28, NVDA at $201.44, and TSM at $439.61, using Yahoo Finance’s ASML chart feed, Yahoo Finance’s Nvidia chart feed, and Yahoo Finance’s TSMC chart feed.
• Polymarket priced a 19% chance of an AI bubble burst in 2026 as of 2026-06-23, according to Polymarket. That is sentiment color only.

What EUV actually bottlenecks

Extreme ultraviolet lithography is the process used to print the smallest features on advanced chips. The machine does not make a finished GPU by itself. It prints patterns at the frontier node. The wafer still needs deposition, etch, metrology, packaging, testing, and a long list of process steps that do not fit in a clean headline.

But EUV matters because frontier logic is where AI accelerators live. Nvidia (NVDA) depends on TSMC (TSM) for leading-edge manufacturing. AMD (AMD) is pushing accelerators into the same capacity pool. Broadcom (AVGO) and other custom silicon designers are competing for advanced-node allocation. Apple (AAPL) also competes for the same foundry ecosystem when high-end mobile chips move through leading nodes.

That makes ASML the upstream choke point. If ASML cannot build enough tools, TSMC cannot expand leading-edge wafer starts as quickly as customers want. If TSMC cannot expand wafer starts, Nvidia and AMD can have strong demand and still face allocation limits.

The market understands the scarcity. ASML’s Q4 2025 order book is the evidence. A €38.8 billion ($42.3 billion) backlog and €7.4 billion ($8.1 billion) of quarterly EUV bookings are not normal industrial-tool numbers, ASML’s Q4 2025 release shows. They are evidence that customers want more frontier capacity than the supply chain can deliver quickly.

The Patel model is useful, but don’t confuse it with guidance

Patel’s model is valuable because it forces the AI debate back to physical units. How many EUV tools? How many wafers? How many accelerator dies? How many gigawatts of deployed compute?

The problem is that the most clickable version turns an analyst model into a hard prophecy. Patel’s 3.5-tools-per-gigawatt ratio and 200 gigawatt ceiling are scenario math, not ASML guidance. ASML does not publish an official 2030 EUV unit target in the checked public materials. The company does publish revenue, backlog, bookings, and sales guidance. Those official numbers prove tight demand. They do not prove the exact 200 gigawatt ceiling.

That distinction matters for investors. A good bottleneck model gives you a watchlist. A bad one becomes a slogan.

ASML’s annual-report financials support the broad demand story. AI investment is lifting EUV demand and installed-base revenue. But official filings do not settle the question of whether EUV, power, packaging, HBM memory, or model efficiency becomes the binding constraint first.

Evidence quality: what is proven and what is still a model

The table below separates official ASML evidence from market signals and analyst assumptions. It uses ASML’s Q4 2025 release, the Dwarkesh interview transcript, and public market data checked on 2026-06-23.

Claim or signal	Evidence	What it proves	What it does not prove
ASML demand is tight	€38.8B ($42.3B) backlog at end-2025	Customers are ordering more lithography capacity than ASML can quickly satisfy	The exact 2030 EUV unit ceiling
EUV demand is concentrated	€7.4B ($8.1B) of Q4 2025 EUV bookings	EUV is a large share of incremental demand	That EUV is the first bottleneck to bind
ASML is still growing	2026 sales guide of €34B ($37.1B) to €39B ($42.5B)	Management expects another growth year	Unlimited production capacity
Patel’s AI compute model	3.5 EUV tools per GW and about 200 GW by 2030	A concrete unit-count framework	ASML guidance or industry consensus
ASML options positioning	74.8 IV rank and 88.4 IV percentile on 2026-06-18	The options market was pricing event risk	Direction or correctness of the EUV thesis

The takeaway is blunt: the official data supports scarcity. It does not support certainty.

The bottleneck is already migrating

The strongest counterpoint is TSMC. If EUV scarcity were the only story, the winning strategy would be simple: buy every available machine, accept the cost, and keep shrinking nodes.

That is not what the industry is doing. TSMC is pushing hard into chiplets, 3D stacking, and CoWoS advanced packaging. The goal is to increase compute per package without depending only on smaller features. TrendForce’s coverage of lithography alternatives points to the same broader pattern: when the lithography path gets blocked, the industry searches for routes around it.

This is the part I would not underweight. Semiconductors have a long history of moving the constraint up the stack. When classic lithography scaling got harder, multi-patterning bought time. When monolithic die economics got worse, chiplets became more attractive. When compute demand surged faster than wafer supply, packaging became strategic infrastructure.

That does not make EUV irrelevant. It makes EUV one bottleneck in a moving system.

Where the pressure lands by company

This is the investable part of the discussion. The table below maps the constraint to the companies most exposed. It uses ASML’s Q4 2025 release, Yahoo Finance’s ASML chart feed, public prices checked on 2026-06-23, and the article’s options check as of 2026-06-18.

Company	Constraint exposure	Public market marker	Investment read-through
ASML	Sole EUV supplier, capacity-constrained	$1,778.28 on 2026-06-23	Scarcity supports backlog and pricing power, but production capacity limits upside speed
TSM	Foundry allocation, packaging capacity, customer prioritization	$439.61 on 2026-06-23	Better positioned if packaging shifts the bottleneck away from pure EUV tool count
NVDA	Needs advanced foundry supply for frontier accelerators	$201.44 on 2026-06-23	Demand can be strong while supply remains rationed
AMD	Competes for AI accelerator allocation	$519.84 on 2026-06-23	Product gains still need foundry and packaging access
AVGO	Custom AI silicon competes for leading-edge capacity	$381.95 on 2026-06-23	Beneficiary of custom-chip demand, but not immune to capacity allocation
MU	AI memory upcycle, less direct EUV exposure	$1,055.73 on 2026-06-23	HBM and memory bandwidth may become separate bottlenecks

The table is not a buy list. It is a map of where the bottleneck changes earnings sensitivity. ASML benefits from scarcity but cannot instantly turn scarcity into unit growth. TSM benefits if packaging becomes the layer that matters most. NVDA, AMD, and AVGO need capacity allocation as much as they need end demand. MU sits in the memory side of the AI stack, where bandwidth can become its own constraint.

The software counterweight

There is another reason the hard-ceiling story can break. AI systems do not stand still while chip supply tightens.

A November 2025 Stanford Hazy Research study found that AI inference intelligence per watt improved 5.3 times from 2023 to 2025, with 3.1 times from model improvements and 1.7 times from hardware gains. If software keeps reducing the compute needed per unit of output, then a fixed EUV tool supply supports more AI service capacity than a static hardware model implies.

That does not mean software solves the bottleneck. It means demand is not a fixed input. The number of GPUs needed to serve a product can fall even while product usage rises. The EUV ceiling then becomes a race between physical tool output, packaging gains, memory bandwidth, grid power, and model efficiency.

My view: Patel is right to force the debate into physical constraints. The market is wrong if it treats one constraint as permanent.

What this does not tell you

This evidence does not tell you that AI infrastructure stops at 200 gigawatts. It tells you that one credible model points to a physical constraint if tool counts, wafer demand, and architecture stay close to today’s path.

It also does not tell you that ASML captures all the economics. Scarcity helps ASML, but manufacturing EUV tools is slow and complex. The company can have extraordinary demand and still grow units gradually. Scarcity can support valuation, but it can also disappoint investors who expect software-like acceleration from a hardware supply chain.

It does not tell you that Nvidia is doomed by allocation. Nvidia can still win if it gets preferred foundry access, improves architecture, shifts workloads, or captures more value per scarce wafer. The bottleneck raises the importance of allocation, not just demand.

And it does not tell you that TSMC has solved the problem. Packaging capacity, CoWoS expansion, HBM supply, and power delivery can each become the next constraint. The industry may route around EUV only to run into another wall.

What I would track next

Start with ASML’s actual EUV shipments and bookings. Backlog is useful, but shipments decide the physical ceiling.

Then watch TSMC’s packaging capacity language. If management keeps emphasizing CoWoS and 3D packaging over High-NA production adoption, that supports the bottleneck-migration view.

Watch HBM supply and memory pricing. AI accelerators without enough high-bandwidth memory are not useful at frontier scale. That is where Micron (MU), SK Hynix, and Samsung matter.

Finally, watch model efficiency. If inference efficiency keeps improving at a 2023 to 2025 pace, the demand side of the EUV equation changes. Not because AI demand disappears, but because each watt and each wafer can do more work.

FAQ

What is EUV lithography?

EUV lithography is a chipmaking process that uses extreme ultraviolet light to print very small patterns on silicon wafers. It is central to advanced logic chips because smaller features can improve performance and energy efficiency.

Why does ASML matter so much?

ASML is the only commercial supplier of EUV lithography systems. Its tools sit upstream of TSMC, Samsung, Intel, Nvidia, AMD, Broadcom, and Apple. If ASML tool supply is tight, advanced-node capacity becomes harder to expand quickly.

Is the 200 gigawatt AI compute cap official guidance?

No. The 200 gigawatt figure is an analyst model associated with Dylan Patel’s EUV bottleneck argument, not ASML guidance. It is useful scenario math, not a company forecast.

Does EUV scarcity automatically make ASML a better stock?

No. Scarcity can support backlog, pricing, and strategic importance, but ASML’s own production capacity limits how fast it can turn demand into revenue. Valuation still matters.

Why does TSMC’s packaging strategy matter?

TSMC’s packaging push matters because it shows the industry is not waiting passively for more EUV machines. Chiplets and advanced packaging can improve compute density even when node shrinks slow down.

Could software efficiency reduce the bottleneck?

Yes, partly. The Stanford Hazy Research study found a 5.3 times improvement in inference intelligence per watt from 2023 to 2025. If that continues, the same chip supply can serve more AI output than static hardware-demand models assume.